A plurality of semiconductor device (transistors) are integrated on a semiconductor substrate, and are separated by separating grooves filled with, for instance, BPSG (boro-phospho-silicate glass). The device includes a gate oxide layer grown on the substrate to insulate a gate from the substrate, a polycrystal layer grown on the gate oxide layer, and an interconnection pattern such as tungsten silicide provided on the polycrystal layers and selectively on the separating grooves.
In fabrication, first, the gate oxide layer, the polycrystal silicon layer and a first BPSG (boro-phospho-silicate glass) layer are successively grown on the silicon substrate. Then, a photo resist layer is formed on the first BPSG layer, and patterned to have a opening for the separating region. After that, the first BPSG layer, the polycrystal silicon layer and the gate oxide layer are etched with using the photo resist layer as a mask, so that a surface of the silicon substrate corresponding to the separating region is exposed.
Next, after removing the photo resist layer, the silicon substrate is etched with using the first BPSG layer as a mask to have grooves to be for the separating regions. Then, a second BPSG (boro-phospho-silicate glass) layer is formed on a whole surface of the fabricated silicon substrate by the CVD (chemical vapor deposition) method, and is reflowed by thermal treatment, so that the grooves are filled up thereby.
Next, the first and second BPSG layers are etched with using the polycrystal silicon layer as a stopper, so that the separating region is formed in the grooves by the remained second BPSG layer. Finally, the tungsten silicide pattern is formed on a surface of the structure as electrodes.
According to the conventional semiconductor device, however, there is a disadvantage in that the silicon substrate may be exposed at an inner surface of the grooves, when the BPSG layers are etched. That is, the second BPSG layer is etched to a level under the surface level of the gate oxide layer, because control of etching depth is not precisely carried out. Therefore, a short circuit may occur between the silicon substrate and the electrode, as the result, reliability of the semiconductor device is decreased to lower yield.